1. Technical Field
The present invention relates generally to the production of Copper-Invar.TM.-Copper (hereinafter "CIC") material, used in High Performance Chip Carriers (hereinafter "HPCC"), and more particularly, to CIC material having improved resistivity control following high temperature exposures.
2. Related Art
Laminate chip carriers demonstrate the potential of providing the semiconductor industry with high performance, low cost first level packaging. However, packaging assemblies that utilize laminate chip carriers may have poor reliability, due to the mismatch of the Coefficient of Thermal Expansion (hereinafter CTE) between the silicon chips and the first level packaging. If the CTE of the first level package closely matches the CTE of the silicon chip (approximately 3 ppm/.degree. C.), minimal stresses are induced at the interface of these layers. However, the stresses at the interface of the first level and second level may be high, thereby yielding a less reliable package. If the CTE of the first level package matches the CTE of the second level package (approximately 18 ppm/.degree. C.), the stresses will be concentrated at the interface of the silicon chip and the first level carrier. A laminate package containing CIC may be used which has an intermediate CTE (approximately 12 ppm/.degree. C.), which yields an assembly with more balanced stresses and improved reliability. The beneficial effects of the CIC are attributable to the low CTE of the INVAR.TM., an alloy containing approximately 63.8% iron, 36% nickel and 0.2% carbon.
Although the theoretical electrical conductivity of copper layers in thin CIC is sufficient for use in laminate packaging, CIC has been observed to exhibit reduced conductivity after high temperature processing. This is believed to be caused by the diffusion of nickel, originating from the INVAR.TM., into the copper layers during heat cycles.
Currently, CIC materials are manufactured using a cladding process in which copper is bonded to the INVAR.TM. surface at their desired final thickness ratios. The CIC substrate is then rolled, under controlled temperature and pressure, to achieve the final desired thickness. Although this method produces well bonded materials with controlled material ratios, it is time consuming and requires the use of extreme pressures and temperatures, which contribute to the internal stresses within the material. These additional stresses may subsequently be removed by heat treatment procedures, which in turn increase the resistivity of the CIC due to the diffusion of nickel into the copper.
Therefore, there exists a need to develop a laminant chip carrier containing CIC which maintains the electrical conductivity of the constituent copper. Currently, there exists no technique designed to reduce the stresses within the CIC material without increasing the resistivity of the copper.